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HOME > NXP Device >ARM7 >LPC2364/66/68  


Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN


NXP사의 LPC2364/66/68은 USB 호스트, CAN, SDRAM, 온 칩 플래시와 같은 고대역폭 주변장치의 동시 운영을 실현하는 두 개의 ARM 고속 버스(AHB: ARM high-speed buses)를 갖춘 ARM7 Core 기반의 MCU입니다.

Microcontroller with 128KB flash, USB 2.0, 10/100 ethernet, I 2 S, real-time emulation, accelerator architecture
Microcontroller with 256KB flash, USB 2.0, 10/100 ethernet, I 2 S, real-time emulation, accelerator architecture
Microcontroller with 512KB flash, USB 2.0, 10/100 ethernet, SD/MMC, I 2 S, real-time emulation, accelerator architecture

< Key Features >

  • ARM7TDMI-S processor, running at up to 72 MHz.
  • Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.
  • 8/32 kB of SRAM on the ARM local bus for high performance CPU access.
  • 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
  • 8 kB SRAM for general purpose DMA use also accessible by the USB.
  • Dual Advanced High-performance Bus (AHB) system that provides for simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem.
  • Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
  • General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial interfaces, the I 2 S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port, as well as for memory-to-memory transfers.
  • Serial interfaces:
    • Ethernet MAC with associated DMA controller. These functions reside on an independent AHB bus.
    • USB 2.0 full-speed device with on-chip PHY and associated DMA controller.
    • Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO.
    • CAN controller with two channels.
    • SPI controller.
    • Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA controller.
    • Three I 2 C-bus interfaces (one with open-drain and two with standard port pins).
    • I 2 S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.
  • Other peripherals:
    • SD/MMC memory card interface (LPC2368 only).
    • 70 general purpose I/O pins with configurable pull-up/down resistors.
    • 10-bit ADC with input multiplexing among 6 pins.
    • 10-bit DAC.
    • Four general purpose timers/counters with a total of 8 capture inputs and 10 compare outputs. Each timer block has an external count input.
    • One PWM/timer block with support for three-phase motor control. The PWM has two external count inputs.
    • Real-Time Clock (RTC) with separate power pin, clock source can be the RTC oscillator or the APB clock.
    • 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off.
    • WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
  • Standard ARM test/debug interface for compatibility with existing tools.
  • Emulation trace module supports real-time trace.
  • Single 3.3 V power supply (3.0 V to 3.6 V).
  • Four reduced power modes: idle, sleep, power-down, and deep power-down.
  • Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources.
  • Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt).
  • Two independent power domains allow fine tuning of power consumption based on needed features.
  • Each peripheral has its own clock divider for further power saving.
  • Brownout detect with separate thresholds for interrupt and forced reset.
  • On-chip power-on reset.
  • On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
  • 4 MHz internal RC oscillator trimmed to 1 pct accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run.
  • On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
  • Versatile pin function selections allow more possibilities for using on-chip peripheral functions.

< Block Diagram >

< Pinning >

< Memory Map >

Ordering Code
LPC2364FBD100 9352 824 63551
LPC2366FBD100 9352 824 62551
LPC2368FBD100 9352 824 61551
- Application Notes -  
- AN10256-2 Using IAP for LPC2000 ARM devices
- AN10403_1; Connecting ethernet interface with LPC2000
- AN10413_2; uC/OS-II Time Management in LPC2000
- AN10576_1; Migrating to the LPC2300/2400 family
- Support Documents-  
- 75015812; 72MHz, 32-bit microcontroller with ARM7 LPC23xx
- 75016051: The choice for embedded Technologies
- Errata Sheet (LPC2364)
- Errata Sheet (LPC2366)
- Errata Sheet (LPC2368)
- LPC2364/66/68/78 User Manual
- Literature LPC23xx
- LPC23xx, LPC24xx PLL Parameter Calculator
- Technical Notes -  
- TN05007 LPC2xxx UART Transmitter Code Example
- TN06001 LPC2xxx SPI Master Code Example
- TN06002 LPC2000 EINT Code Example
- TN06004 LPC2000 ADC Code Example
- LPC2000 I2C Slave Code Example
- LPC2000 USB Design Guide Line
- UUencode

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