16/32bit ARM 9 Core

    16/32bit ARM 7 Core

    8bit 80C51 Core

HOME > NXP Device >ARM7 >LPC2468  


Microcontroller with dual AHB accelerator architecture, 512KB flash, USB 2.0 device/host/OTG, 10/100 ethernet, SD/MMC, I2S, real-time emulation, external memory interface


16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. The LPC2468 has 512 kB of on-chip high-speed flash memory

MCU with dual AHB accelerator architecture, 512KB flash, USB 2.0 device/host/OTG, 10/100 ethernet, SD/MMC, I2S, real-time emulation, external memory interface

< Key Features >

  • ARM7TDMI-S processor, running at up to 72 MHz.
  • 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.
  • 98 kB on-chip SRAM includes:
    • 64 kB of SRAM on the ARM local bus for high performance CPU access.
    • 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
    • 16 kB SRAM for general purpose DMA use also accessible by the USB.
    • 2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
  • Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention.
  • EMC provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as Single Data Rate SDRAM.
  • Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
  • General Purpose AHB DMA controller (GPDMA) that can be used with the SSP, I2S-bus, and SD/MMC interface as well as for memory-to-memory transfers.
  • Serial Interfaces:
    • Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB bus.
    • USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and associated DMA controller.
    • Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO.
    • CAN controller with two channels.
    • SPI controller.
    • Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.
    • Three I2C-bus interfaces (one with open-drain and two with standard port pins).
    • I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.
  • Other peripherals:
    • SD/MMC memory card interface.
    • 160 General purpose I/O pins with configurable pull-up/down resistors.
    • 10-bit ADC with input multiplexing among 8 pins.
    • 10-bit DAC.
    • Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input.
    • Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count inputs.
    • RTC with separate power domain, clock source can be the RTC oscillator or the APB clock.
    • 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off.
    • WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
  • Standard ARM test/debug interface for compatibility with existing tools.
  • Emulation trace module supports real-time trace.
  • Single 3.3 V power supply (3.0 V to 3.6 V).
  • Three reduced power modes: idle, sleep, and power-down.
  • Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources.
  • Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt).
  • Two independent power domains allow fine tuning of power consumption based on needed features.
  • Each peripheral has its own clock divider for further power saving. These dividers help reducing active power by 20 - 30 pct.
  • Brownout detect with separate thresholds for interrupt and forced reset.
  • On-chip power-on reset.
  • On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
  • 4 MHz internal RC oscillator trimmed to 1 pct accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run.
  • On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
  • Boundary scan for simplified board testing.
  • Versatile pin function selections allow more possibilities for using on-chip peripheral functions.

< Block Diagrams >

< Pinning >

< Pinning LQFP208 package >

< Comparison Table >

Ordering Code
LPC2468FBD208 9352 824 57551
LPC2468FET208 9352 832 34551
- Application Notes -  
- AN10256-2 Using IAP for LPC2000 ARM devices
- AN10403_1; Connecting ethernet interface with LPC2000
- AN10413_2; uC/OS-II Time Management in LPC2000
- AN10513_1; Brushed DC motor control using the LPC2101
- AN10548_1: Getting started with LPC288x
- AN10576_1; Migrating to the LPC2300/2400 family
- AN10583_1: Realizing an MP3 player with the LPC2148, using libmad and EFSL
- AN10661_1; Brushless DC motor control using the LPC2141
- AN10674_1; NXP LPC2000 CAN driver with FullCAN mode
- AN10689_1; Full-duplex software UART for LPC2000
- Support Documents-  
- 75015914; 72-MHz, 32-bit microcontroller with ARM7TDMI-S(tm) core LPC24xx
- Design_example_IEC_alarm; Design example IEC alarm
- Errata sheet LPC2468
- LPC24XX User Manual


본사. 121-703 서울시 마포구 마포대로4다길 18 (마포동) 1302호 | Tel. 02-704-7111 | Fax. 02-704-7211
매장. 152-721 서울시 구로구 경인로53길 15 (구로동) 가동 2315호 | Tel. 02-6679-1400 | Mob. 010-5703-7111
Copyright ⓒ 1996 - 2014 VAS Corporation, All Rights Reserved.